1. Field
Example embodiments relate to a test device and a semiconductor integrated circuit device, and more particularly, to a test device and a semiconductor integrated circuit device having improved productivity.
2. Description of the Prior Art
A static random access memory (hereinafter referred to as an SRAM) has a memory capacity that is relatively smaller than that of a dynamic random access memory (hereinafter referred to as a DRAM), but its operating speed is relatively higher than that of the DRAM. Accordingly, the SRAM is widely used as cache memory for computers requiring a high-speed operation and in portable appliances.
SRAM cells are classified into thin film transistor (TFT) cells and full complementary metal oxide semiconductor (FCMOS) cells. The full FCMOS cell includes a plurality of pull-up transistors and pull-down transistors that constitute a latch, and a plurality of pass transistors for accessing the latch.
With the integration of a semiconductor memory device, the size of a memory cell has gradually become smaller causing the size of metal contacts to also become smaller. As the size of the contacts becomes smaller, patterning the contacts accurately may become difficult, and thus, relatively inferior or defective contacts may be formed. Particularly, in the case of shared contacts formed on the SRAM cells, bridges, through which adjacent shared contacts are electrically connected to each other, may be produced.
In order to determine whether bridges are produced between shared contacts, nodes, which are connected to the respective adjacent shared contacts, are formed. A voltage may be applied to the nodes which may cause a current to flow from one node to another. However, current may flow between the nodes by other means, for example, a short circuit between adjacent active regions, a short circuit between a contact and a gate line, and/or a short circuit between nodes.